From 95fd6ae836ab5fee7387f4df46b727165a05b723 Mon Sep 17 00:00:00 2001 From: Paul Oliver Date: Thu, 25 Jun 2026 04:42:23 +0200 Subject: Adds v1 unit tests and fixes bugs found by them --- test/ui/v1/1rops/ui.c | 64 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 test/ui/v1/1rops/ui.c (limited to 'test/ui/v1/1rops/ui.c') diff --git a/test/ui/v1/1rops/ui.c b/test/ui/v1/1rops/ui.c new file mode 100644 index 0000000..9c96470 --- /dev/null +++ b/test/ui/v1/1rops/ui.c @@ -0,0 +1,64 @@ +#if !defined(COMMAND_NEW) +#error +#endif + +int main(void) { + salis_init(); + + while (mvec_is_proc_owner(g_cores, g_cores->pvec->ip, g_cores->pcur)) { + uint8_t inst = mvec_get_inst(g_cores, g_cores->pvec->ip); + + if (inst != incn && inst != decn && inst != notn && inst != shfl && inst != shfr && inst != zero && inst != unit) { + salis_step(1); + continue; + } + + uint64_t *reg = &g_cores->pvec->r0x; + + switch (mvec_get_inst(g_cores, g_cores->pvec->ip + 1)) { + case nop0: + reg = &g_cores->pvec->r0x; + break; + case nop1: + reg = &g_cores->pvec->r1x; + break; + case nop2: + reg = &g_cores->pvec->r2x; + break; + case nop3: + reg = &g_cores->pvec->r3x; + break; + } + + uint64_t reg_val = *reg; + + salis_step(1); + + switch (inst) { + case incn: + assert(*reg == reg_val + 1); + break; + case decn: + assert(*reg == reg_val - 1); + break; + case notn: + assert(*reg == !reg_val); + break; + case shfl: + assert(*reg == reg_val << 1); + break; + case shfr: + assert(*reg == reg_val >> 1); + break; + case zero: + assert(*reg == 0); + break; + case unit: + assert(*reg == 1); + break; + } + } + + salis_free(); + return 0; +} -- cgit v1.2.1