#if !defined(COMMAND_NEW)
#error
#endif

int main(void) {
    salis_init();

    while (mvec_is_proc_owner(g_cores, g_cores->pvec->ip, g_cores->pcur)) {
        uint8_t inst = mvec_get_inst(g_cores, g_cores->pvec->ip);

        if (inst != load && inst != wrte) {
            salis_step(1);
            continue;
        }

        uint64_t *regs[2] = {
            &g_cores->pvec->r0x,
            &g_cores->pvec->r0x,
        };

        for (uint64_t i = 0; i < 2; i++) {
            uint8_t rmod = mvec_get_inst(g_cores, g_cores->pvec->ip + 1 + i);
            if (rmod == nop0) regs[i] = &g_cores->pvec->r0x;
            else if (rmod == nop1) regs[i] = &g_cores->pvec->r1x;
            else if (rmod == nop2) regs[i] = &g_cores->pvec->r2x;
            else if (rmod == nop3) regs[i] = &g_cores->pvec->r3x;
            else break;
        }

        if (g_cores->pvec->sp != *regs[0]) {
            salis_step(1);
            continue;
        }

        uint64_t reg_vals[2] = {*regs[0], *regs[1]};

        assert(g_cores->pvec->sp == *regs[0]);
        salis_step(1);
        assert(g_cores->pvec->sp == g_cores->pvec->ip);

        switch (inst) {
        case load:
            assert(*regs[1] == (uint64_t)mvec_get_inst(g_cores, reg_vals[0]));
            break;
        case wrte:
            assert(*regs[0] == reg_vals[0]);
            assert(*regs[1] == reg_vals[1]);
            assert(mvec_get_inst(g_cores, *regs[0]) == *regs[1] % INST_CAP);
            break;
        }
    }

    salis_free();
    return 0;
}