From 1961b4b237083f4cfac9ca6b249c1d6cb665d149 Mon Sep 17 00:00:00 2001
From: Paul Oliver <contact@pauloliver.dev>
Date: Tue, 14 Jul 2026 17:29:02 +0200
Subject: Initial (refactor)

---
 test/ui/v1/2rops/links.json |  1 +
 test/ui/v1/2rops/ui.c       | 56 +++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 57 insertions(+)
 create mode 100644 test/ui/v1/2rops/links.json
 create mode 100644 test/ui/v1/2rops/ui.c

(limited to 'test/ui/v1/2rops')

diff --git a/test/ui/v1/2rops/links.json b/test/ui/v1/2rops/links.json
new file mode 100644
index 0000000..fe51488
--- /dev/null
+++ b/test/ui/v1/2rops/links.json
@@ -0,0 +1 @@
+[]
diff --git a/test/ui/v1/2rops/ui.c b/test/ui/v1/2rops/ui.c
new file mode 100644
index 0000000..e74172b
--- /dev/null
+++ b/test/ui/v1/2rops/ui.c
@@ -0,0 +1,56 @@
+// file    : test/ui/v1/2rops/ui.c
+// project : Salis-VM
+// author  : Paul Oliver <contact@pauloliver.dev>
+
+#include <assert.h>
+#include <stdint.h>
+#include <threads.h>
+#include <zlib.h>
+
+#include "arch_spec.h"
+#include "arch_inst.h"
+#include "compress.h"
+#include "salis.h"
+
+int main(void) {
+    salis_init();
+
+    while (mvec_is_proc_owner(g_cores, g_cores->pvec->ip, g_cores->pcur)) {
+        uint8_t inst = mvec_get_inst(g_cores, g_cores->pvec->ip);
+
+        if (inst != rdup && inst != rswp) {
+            salis_step(1);
+            continue;
+        }
+
+        uint64_t *regs[2] = {
+            &g_cores->pvec->r0x,
+            &g_cores->pvec->r0x,
+        };
+
+        for (uint64_t i = 0; i < 2; i++) {
+            uint8_t rmod = mvec_get_inst(g_cores, g_cores->pvec->ip + 1 + i);
+            if (rmod == nop0) regs[i] = &g_cores->pvec->r0x;
+            else if (rmod == nop1) regs[i] = &g_cores->pvec->r1x;
+            else if (rmod == nop2) regs[i] = &g_cores->pvec->r2x;
+            else if (rmod == nop3) regs[i] = &g_cores->pvec->r3x;
+            else break;
+        }
+
+        uint64_t reg_vals[2] = {*regs[0], *regs[1]};
+        salis_step(1);
+
+        switch (inst) {
+        case rdup:
+            assert(*regs[1] == reg_vals[0]);
+            break;
+        case rswp:
+            assert(*regs[0] == reg_vals[1]);
+            assert(*regs[1] == reg_vals[0]);
+            break;
+        }
+    }
+
+    salis_save_and_free();
+    return 0;
+}
-- 
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