test/ui/v1/1rops/ui.c


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74

// file    : test/ui/v1/1rops/ui.c
// project : Salis-VM
// author  : Paul Oliver <contact@pauloliver.dev>

#include <assert.h>
#include <stdint.h>
#include <threads.h>
#include <zlib.h>

#include "arch_spec.h"
#include "arch_inst.h"
#include "compress.h"
#include "salis.h"

int main(void) {
    salis_init();

    while (mvec_is_proc_owner(g_cores, g_cores->pvec->ip, g_cores->pcur)) {
        uint8_t inst = mvec_get_inst(g_cores, g_cores->pvec->ip);

        if (inst != incn && inst != decn && inst != notn && inst != shfl && inst != shfr && inst != zero && inst != unit) {
            salis_step(1);
            continue;
        }

        uint64_t *reg = &g_cores->pvec->r0x;

        switch (mvec_get_inst(g_cores, g_cores->pvec->ip + 1)) {
        case nop0:
            reg = &g_cores->pvec->r0x;
            break;
        case nop1:
            reg = &g_cores->pvec->r1x;
            break;
        case nop2:
            reg = &g_cores->pvec->r2x;
            break;
        case nop3:
            reg = &g_cores->pvec->r3x;
            break;
        }

        uint64_t reg_val = *reg;

        salis_step(1);

        switch (inst) {
        case incn:
            assert(*reg == reg_val + 1);
            break;
        case decn:
            assert(*reg == reg_val - 1);
            break;
        case notn:
            assert(*reg == !reg_val);
            break;
        case shfl:
            assert(*reg == reg_val << 1);
            break;
        case shfr:
            assert(*reg == reg_val >> 1);
            break;
        case zero:
            assert(*reg == 0);
            break;
        case unit:
            assert(*reg == 1);
            break;
        }
    }

    salis_save_and_free();
    return 0;
}