diff options
35 files changed, 1222 insertions, 9 deletions
@@ -97,3 +97,18 @@ user@host$ ./salis.py client -o -i ${SERVER_IP} - ImGui - ImPlot - OpenGL + +## Unit tests +A set of unit tests are included in this repo. Run them using the following command: +```console +user@host$ ./salis.py test +``` + +Optionally, you may run a single test (or a test subset) using the `-p` argument: +```console +user@host$ ./salis.py test -p 'test_v1.*' +``` + +Tests will fail in case any needed dependencies are missing, and thus help ensure +the host system is properly configured. Ensure all tests pass before attempting to run +new simulations. diff --git a/arch/v1/vars.py b/arch/v1/vars.py index 4eac4e7..3eb0880 100644 --- a/arch/v1/vars.py +++ b/arch/v1/vars.py @@ -1,3 +1,12 @@ +# index +# [section] instruction set +# [section] core data fields +# [section] other fields +# [section] process fields + +# ------------------------------------------------------------------------------ +# [section] instruction set +# ------------------------------------------------------------------------------ inst_set = [ (["noop"], " "), (["nop0"], "0"), @@ -65,6 +74,9 @@ inst_set = [ (["lokp"], "P"), ] +# ------------------------------------------------------------------------------ +# [section] core data fields +# ------------------------------------------------------------------------------ core_data_fields = [ ("uint64_t", f"ipop[{len(inst_set)}]"), # instruction population counter ("uint64_t", f"iexe[{len(inst_set)}]"), # instruction execution counter @@ -75,9 +87,17 @@ core_data_fields = [ ("uint64_t", f"weva[{2 ** globals()["args"].mvec_pow}]"), # write events array ("uint64_t", f"xeva[{2 ** globals()["args"].mvec_pow}]"), # memory block swap events array ] + +# ------------------------------------------------------------------------------ +# [section] other fields +# ------------------------------------------------------------------------------ core_fields = [] muta_flip = False mvec_loop = False + +# ------------------------------------------------------------------------------ +# [section] process fields +# ------------------------------------------------------------------------------ proc_fields = [ ("uint64_t", "ip"), ("uint64_t", "sp"), diff --git a/core/salis.c b/core/salis.c index dac9e52..bf7ec44 100644 --- a/core/salis.c +++ b/core/salis.c @@ -506,6 +506,7 @@ void core_init(struct Core *core, uint64_t *seed) { core->pnum = CLONES; core->pcap = CLONES; core->plst = CLONES - 1; + core->pcur = CLONES - 1; core->iviv = calloc(SYNC_INTERVAL, sizeof(uint8_t)); core->ivav = calloc(SYNC_INTERVAL, sizeof(uint64_t)); core->pvec = calloc(core->pcap, sizeof(struct Proc)); @@ -989,6 +990,12 @@ void salis_run_thread(uint64_t ns) { } void salis_sync(void) { +#if !defined(NDEBUG) + for (int i = 0; i < CORES; ++i) { + assert(g_cores[i].ivpt == SYNC_INTERVAL); + } +#endif + uint8_t *iviv0 = g_cores[0].iviv; uint64_t *ivav0 = g_cores[0].ivav; diff --git a/test/anc/v1/1rops.asm b/test/anc/v1/1rops.asm new file mode 100644 index 0000000..e717aef --- /dev/null +++ b/test/anc/v1/1rops.asm @@ -0,0 +1,105 @@ +incn +incn +nop0 +incn +nop1 +nop2 +incn +nop2 +nop3 +nop0 +incn +nop3 + +noop + +decn +decn +nop0 +decn +nop1 +nop2 +decn +nop2 +nop3 +nop0 +decn +nop3 + +noop + +incn +incn +incn +notn +notn +nop0 +notn +nop1 +nop2 +notn +nop2 +nop3 +nop0 +notn +nop3 + +noop + +shfl +shfl +nop0 +shfl +nop1 +nop2 +shfl +nop2 +nop3 +nop0 +shfl +nop3 + +noop + +shfr +shfr +nop0 +shfr +nop1 +nop2 +shfr +nop2 +nop3 +nop0 +shfr +nop3 + +noop + +zero +zero +nop0 +zero +nop1 +nop2 +zero +nop2 +nop3 +nop0 +zero +nop3 + +noop + +unit +unit +nop0 +unit +nop1 +nop2 +unit +nop2 +nop3 +nop0 +unit +nop3 diff --git a/test/anc/v1/2rops.asm b/test/anc/v1/2rops.asm new file mode 100644 index 0000000..4060285 --- /dev/null +++ b/test/anc/v1/2rops.asm @@ -0,0 +1,22 @@ +incn +incn +incn + +noop + +dupl +nop0 +nop1 +dupl +nop2 +dupl +nop1 +nop3 + +noop + +swap +nop1 +swap +nop3 +nop2 diff --git a/test/anc/v1/3rops.asm b/test/anc/v1/3rops.asm new file mode 100644 index 0000000..b8b2895 --- /dev/null +++ b/test/anc/v1/3rops.asm @@ -0,0 +1,81 @@ +incn +addn +addn +nop0 +addn +nop1 +nop0 +addn +nop2 +nop1 +nop0 +addn +nop3 +nop2 +nop1 + +noop + +subn +nop3 +nop2 +nop1 +subn +nop3 +nop2 +subn +nop3 +subn +nop1 +nop2 +subn + +noop + +incn +incn +muln +muln +nop0 +muln +nop1 +nop0 +muln +nop2 +nop1 +nop0 +muln +nop3 +nop2 +nop1 + +noop + +divn +nop3 +nop2 +nop1 +divn +nop3 +nop2 +divn +nop3 +divn +nop1 +nop2 +divn + +noop + +; div by zero == noop +zero +divn +divn +nop1 +divn +nop2 +nop1 +divn +nop3 +nop2 +nop0 diff --git a/test/anc/v1/addrs.asm b/test/anc/v1/addrs.asm new file mode 100644 index 0000000..5031007 --- /dev/null +++ b/test/anc/v1/addrs.asm @@ -0,0 +1,71 @@ +lokb +lokd +lokf +lokh +lokj +lokl +lokn +lokp + +noop +noop + +adrf +keya +adrb +keyb +nop1 +adrf +keyc +nop2 +adrb +keyd +nop3 +adrf +keye +nop0 +adrb +keyf +nop1 +adrf +keyg +nop2 +adrb +keyh +nop3 +adrf +keyi +nop0 +adrb +keyj +nop1 +adrf +keyk +nop2 +adrb +keyl +nop3 +adrf +keym +nop0 +adrb +keyn +nop1 +adrf +keyo +nop2 +adrb +keyp +nop3 + +noop +noop + +loka +lokc +loke +lokg +loki +lokk +lokm +loko diff --git a/test/anc/v1/allos.asm b/test/anc/v1/allos.asm new file mode 100644 index 0000000..4c04a0f --- /dev/null +++ b/test/anc/v1/allos.asm @@ -0,0 +1,27 @@ +incn +shfl +shfl + +allf +nop0 +nop1 +allf +allb +splt +splt +splt + +allf +nop0 +nop1 +allb +allf +splt +splt + +allb +nop0 +nop1 +allb +allf +splt diff --git a/test/anc/v1/ifnzs.asm b/test/anc/v1/ifnzs.asm new file mode 100644 index 0000000..a40f4dc --- /dev/null +++ b/test/anc/v1/ifnzs.asm @@ -0,0 +1,46 @@ +ifnz +incn +incn +ifnz +nop0 +incn +nop0 + +noop + +ifnz +nop1 +incn +nop1 +incn +nop1 +ifnz +nop1 +incn +nop1 + +noop + +ifnz +nop2 +incn +nop2 +incn +nop2 +ifnz +nop2 +incn +nop2 + +noop + +ifnz +nop3 +incn +nop3 +incn +nop3 +ifnz +nop3 +incn +nop3 diff --git a/test/anc/v1/ioops.asm b/test/anc/v1/ioops.asm new file mode 100644 index 0000000..539715e --- /dev/null +++ b/test/anc/v1/ioops.asm @@ -0,0 +1,100 @@ +keya +lokb +keyc +lokd +keye +lokf +keyg +lokh + +noop + +incn +nop1 +incn +nop2 +incn +nop2 +incn +nop3 +incn +nop3 +incn +nop3 +pshn +pshn +nop1 +pshn +nop2 +pshn +nop3 + +noop + +load +load +nop1 +nop1 +load +nop2 +nop2 +load +nop3 +nop3 + +popn +nop3 +popn +nop2 +popn +nop1 +popn +pshn +pshn +nop1 +pshn +nop2 +pshn +nop3 + +noop + +load +nop2 +nop3 +load +nop1 +nop2 +load +nop0 +nop1 +load + +noop + +muln +nop0 +nop1 +nop2 +muln +nop1 +nop2 +nop3 +muln +nop2 +nop3 +zero +nop3 + +wrte +nop3 +incn +nop3 +wrte +nop3 +nop1 +incn +nop3 +wrte +nop3 +nop2 diff --git a/test/anc/v1/jumps.asm b/test/anc/v1/jumps.asm new file mode 100644 index 0000000..0f86eda --- /dev/null +++ b/test/anc/v1/jumps.asm @@ -0,0 +1,52 @@ +jmpf +keya +lokb +jmpf +keyc +lokd +jmpf +keye +lokf +jmpf +keyg +lokh +jmpf +keyi +lokj +jmpf +keyk +lokl +jmpf +keym +lokn +jmpf +keyo +lokp + +noop +noop + +loka +jmpb +keyb +lokc +jmpb +keyd +loke +jmpb +keyf +lokg +jmpb +keyh +loki +jmpb +keyj +lokk +jmpb +keyl +lokm +jmpb +keyn +loko +jmpb +keyp diff --git a/test/anc/v1/mbops.asm b/test/anc/v1/mbops.asm new file mode 100644 index 0000000..d586173 --- /dev/null +++ b/test/anc/v1/mbops.asm @@ -0,0 +1,13 @@ +incn +shfl +shfl +allf + +bswp +bswp +bswp + +bclr + +bswp +bclr diff --git a/test/anc/v1/stack.asm b/test/anc/v1/stack.asm new file mode 100644 index 0000000..54c1e7d --- /dev/null +++ b/test/anc/v1/stack.asm @@ -0,0 +1,47 @@ +incn +incn +nop1 +shfl +nop1 +incn +nop2 +shfl +nop2 +shfl +nop2 + +noop + +pshn +pshn +nop1 +pshn +nop2 +pshn +nop3 +pshn +nop0 +pshn +nop1 +pshn +nop2 +pshn +nop3 + +noop + +popn +popn +nop1 +popn +nop2 +popn +nop3 +popn +nop0 +popn +nop1 +popn +nop2 +popn +nop3 diff --git a/test/test_v1.py b/test/test_v1.py index 466e4bd..783dc38 100644 --- a/test/test_v1.py +++ b/test/test_v1.py @@ -2,5 +2,45 @@ from test_general import SalisTest class TestV1(SalisTest): @SalisTest.run_ui_test(anc="noops", anc_path="test/anc", ui="noops", ui_path="test/ui/v1", vm_arch="v1") - def test_ui_v1_noops(self): + def test_noops(self): + pass + + @SalisTest.run_ui_test(anc="jumps", anc_path="test/anc", ui="jumps", ui_path="test/ui/v1", vm_arch="v1") + def test_jumps(self): + pass + + @SalisTest.run_ui_test(anc="addrs", anc_path="test/anc", ui="addrs", ui_path="test/ui/v1", vm_arch="v1") + def test_addrs(self): + pass + + @SalisTest.run_ui_test(anc="ifnzs", anc_path="test/anc", ui="ifnzs", ui_path="test/ui/v1", vm_arch="v1") + def test_ifnzs(self): + pass + + @SalisTest.run_ui_test(anc="allos", anc_path="test/anc", ui="allos", ui_path="test/ui/v1", vm_arch="v1", clones=2) + def test_allos(self): + pass + + @SalisTest.run_ui_test(anc="mbops", anc_path="test/anc", ui="mbops", ui_path="test/ui/v1", vm_arch="v1") + def test_mbops(self): + pass + + @SalisTest.run_ui_test(anc="3rops", anc_path="test/anc", ui="3rops", ui_path="test/ui/v1", vm_arch="v1") + def test_3rops(self): + pass + + @SalisTest.run_ui_test(anc="1rops", anc_path="test/anc", ui="1rops", ui_path="test/ui/v1", vm_arch="v1") + def test_1rops(self): + pass + + @SalisTest.run_ui_test(anc="stack", anc_path="test/anc", ui="stack", ui_path="test/ui/v1", vm_arch="v1") + def test_stack(self): + pass + + @SalisTest.run_ui_test(anc="ioops", anc_path="test/anc", ui="ioops", ui_path="test/ui/v1", vm_arch="v1") + def test_ioops(self): + pass + + @SalisTest.run_ui_test(anc="2rops", anc_path="test/anc", ui="2rops", ui_path="test/ui/v1", vm_arch="v1") + def test_2rops(self): pass diff --git a/test/ui/v1/1rops/ui.c b/test/ui/v1/1rops/ui.c new file mode 100644 index 0000000..9c96470 --- /dev/null +++ b/test/ui/v1/1rops/ui.c @@ -0,0 +1,64 @@ +#if !defined(COMMAND_NEW) +#error +#endif + +int main(void) { + salis_init(); + + while (mvec_is_proc_owner(g_cores, g_cores->pvec->ip, g_cores->pcur)) { + uint8_t inst = mvec_get_inst(g_cores, g_cores->pvec->ip); + + if (inst != incn && inst != decn && inst != notn && inst != shfl && inst != shfr && inst != zero && inst != unit) { + salis_step(1); + continue; + } + + uint64_t *reg = &g_cores->pvec->r0x; + + switch (mvec_get_inst(g_cores, g_cores->pvec->ip + 1)) { + case nop0: + reg = &g_cores->pvec->r0x; + break; + case nop1: + reg = &g_cores->pvec->r1x; + break; + case nop2: + reg = &g_cores->pvec->r2x; + break; + case nop3: + reg = &g_cores->pvec->r3x; + break; + } + + uint64_t reg_val = *reg; + + salis_step(1); + + switch (inst) { + case incn: + assert(*reg == reg_val + 1); + break; + case decn: + assert(*reg == reg_val - 1); + break; + case notn: + assert(*reg == !reg_val); + break; + case shfl: + assert(*reg == reg_val << 1); + break; + case shfr: + assert(*reg == reg_val >> 1); + break; + case zero: + assert(*reg == 0); + break; + case unit: + assert(*reg == 1); + break; + } + } + + salis_free(); + return 0; +} diff --git a/test/ui/v1/1rops/vars.py b/test/ui/v1/1rops/vars.py new file mode 100644 index 0000000..9c2a9f3 --- /dev/null +++ b/test/ui/v1/1rops/vars.py @@ -0,0 +1,3 @@ +flags = set() +defines = set() +links = set() diff --git a/test/ui/v1/2rops/ui.c b/test/ui/v1/2rops/ui.c new file mode 100644 index 0000000..5fcf65f --- /dev/null +++ b/test/ui/v1/2rops/ui.c @@ -0,0 +1,46 @@ +#if !defined(COMMAND_NEW) +#error +#endif + +int main(void) { + salis_init(); + + while (mvec_is_proc_owner(g_cores, g_cores->pvec->ip, g_cores->pcur)) { + uint8_t inst = mvec_get_inst(g_cores, g_cores->pvec->ip); + + if (inst != dupl && inst != swap) { + salis_step(1); + continue; + } + + uint64_t *regs[2] = { + &g_cores->pvec->r0x, + &g_cores->pvec->r0x, + }; + + for (uint64_t i = 0; i < 2; i++) { + uint8_t rmod = mvec_get_inst(g_cores, g_cores->pvec->ip + 1 + i); + if (rmod == nop0) regs[i] = &g_cores->pvec->r0x; + else if (rmod == nop1) regs[i] = &g_cores->pvec->r1x; + else if (rmod == nop2) regs[i] = &g_cores->pvec->r2x; + else if (rmod == nop3) regs[i] = &g_cores->pvec->r3x; + else break; + } + + uint64_t reg_vals[2] = {*regs[0], *regs[1]}; + salis_step(1); + + switch (inst) { + case dupl: + assert(*regs[1] == reg_vals[0]); + break; + case swap: + assert(*regs[0] == reg_vals[1]); + assert(*regs[1] == reg_vals[0]); + break; + } + } + + salis_free(); + return 0; +} diff --git a/test/ui/v1/2rops/vars.py b/test/ui/v1/2rops/vars.py new file mode 100644 index 0000000..9c2a9f3 --- /dev/null +++ b/test/ui/v1/2rops/vars.py @@ -0,0 +1,3 @@ +flags = set() +defines = set() +links = set() diff --git a/test/ui/v1/3rops/ui.c b/test/ui/v1/3rops/ui.c new file mode 100644 index 0000000..e4e2d83 --- /dev/null +++ b/test/ui/v1/3rops/ui.c @@ -0,0 +1,60 @@ +#if !defined(COMMAND_NEW) +#error +#endif + +int main(void) { + salis_init(); + + while (mvec_is_proc_owner(g_cores, g_cores->pvec->ip, g_cores->pcur)) { + uint8_t inst = mvec_get_inst(g_cores, g_cores->pvec->ip); + + if (inst != addn && inst != subn && inst != muln && inst != divn) { + salis_step(1); + continue; + } + + uint64_t *regs[3] = { + &g_cores->pvec->r0x, + &g_cores->pvec->r0x, + &g_cores->pvec->r0x, + }; + + for (uint64_t i = 0; i < 3; i++) { + uint8_t rmod = mvec_get_inst(g_cores, g_cores->pvec->ip + 1 + i); + if (rmod == nop0) regs[i] = &g_cores->pvec->r0x; + else if (rmod == nop1) regs[i] = &g_cores->pvec->r1x; + else if (rmod == nop2) regs[i] = &g_cores->pvec->r2x; + else if (rmod == nop3) regs[i] = &g_cores->pvec->r3x; + else break; + } + + uint64_t reg_vals[3] = {*regs[0], *regs[1], *regs[2]}; + salis_step(1); + uint64_t result = *regs[0]; + + switch (inst) { + case addn: + assert(result == reg_vals[1] + reg_vals[2]); + break; + case subn: + assert(result == reg_vals[1] - reg_vals[2]); + break; + case muln: + assert(result == reg_vals[1] * reg_vals[2]); + break; + case divn: + if (reg_vals[2] != 0) { + assert(result == reg_vals[1] / reg_vals[2]); + } else { + assert(*regs[0] == reg_vals[0]); + assert(*regs[1] == reg_vals[1]); + assert(*regs[2] == reg_vals[2]); + } + + break; + } + } + + salis_free(); + return 0; +} diff --git a/test/ui/v1/3rops/vars.py b/test/ui/v1/3rops/vars.py new file mode 100644 index 0000000..9c2a9f3 --- /dev/null +++ b/test/ui/v1/3rops/vars.py @@ -0,0 +1,3 @@ +flags = set() +defines = set() +links = set() diff --git a/test/ui/v1/addrs/ui.c b/test/ui/v1/addrs/ui.c new file mode 100644 index 0000000..8949c3f --- /dev/null +++ b/test/ui/v1/addrs/ui.c @@ -0,0 +1,47 @@ +#if !defined(COMMAND_NEW) +#error +#endif + +void check_found(uint64_t addr, uint64_t lok, uint64_t regi) { + assert(mvec_get_inst(g_cores, addr - 1) == (regi % 2 == 0 ? adrf : adrb)); + assert(mvec_get_inst(g_cores, (&g_cores->pvec->r0x)[regi]) == lok); +} + +int main(void) { + salis_init(); + uint64_t regi = 0; + + while (mvec_is_proc_owner(g_cores, g_cores->pvec->ip, g_cores->pcur)) { + uint8_t inst = mvec_get_inst(g_cores, g_cores->pvec->ip); + + switch (inst) { +#define CASE(id) \ + case key##id: \ + check_found(g_cores->pvec->ip, lok##id, regi); \ + regi = (regi + 1) % 4; \ + break; + CASE(a) + CASE(b) + CASE(c) + CASE(d) + CASE(e) + CASE(f) + CASE(g) + CASE(h) + CASE(i) + CASE(j) + CASE(k) + CASE(l) + CASE(m) + CASE(n) + CASE(o) + CASE(p) +#undef CASE + } + + salis_step(1); + } + + salis_free(); + return 0; +} diff --git a/test/ui/v1/addrs/vars.py b/test/ui/v1/addrs/vars.py new file mode 100644 index 0000000..9c2a9f3 --- /dev/null +++ b/test/ui/v1/addrs/vars.py @@ -0,0 +1,3 @@ +flags = set() +defines = set() +links = set() diff --git a/test/ui/v1/allos/ui.c b/test/ui/v1/allos/ui.c new file mode 100644 index 0000000..1a02c30 --- /dev/null +++ b/test/ui/v1/allos/ui.c @@ -0,0 +1,90 @@ +#if !defined(COMMAND_NEW) +#error +#endif + +#if CLONES != 2 +#error +#endif + +#define CHILD_SIZE 4 + +void check_new_proc(void) { + const struct Proc *proc = proc_get(g_cores, g_cores->plst); + assert(proc->mb0s == CHILD_SIZE); + assert(proc->mb1a == 0); + assert(proc->mb1s == 0); + assert(proc->r0x == 0); + assert(proc->r1x == 0); + assert(proc->r2x == 0); + assert(proc->r3x == 0); + assert(proc->s0 == 0); + assert(proc->s1 == 0); + assert(proc->s2 == 0); + assert(proc->s3 == 0); + assert(proc->s4 == 0); + assert(proc->s5 == 0); + assert(proc->s6 == 0); + assert(proc->s7 == 0); + + uint64_t birth_addr = (uint64_t)-1; + + switch (g_cores->plst) { + case 2: + birth_addr = ANC_SIZE; + break; + case 3: + birth_addr = ANC_SIZE + (MVEC_SIZE / 2); + break; + case 4: + birth_addr = ANC_SIZE + CHILD_SIZE; + break; + case 5: + birth_addr = ANC_SIZE + CHILD_SIZE + (MVEC_SIZE / 2); + break; + case 6: + birth_addr = (MVEC_SIZE / 2) - CHILD_SIZE; + break; + default: + assert(false); + } + + assert(proc->ip == birth_addr); + assert(proc->sp == birth_addr); + assert(proc->mb0a == birth_addr); +} + +int main(void) { + salis_init(); + + while (mvec_is_proc_owner(g_cores, proc_fetch(g_cores, 1)->ip, 1)) { + const struct Proc *proc_next = proc_get(g_cores, (g_cores->pcur + 1) % g_cores->pnum); + bool will_split = mvec_get_inst(g_cores, proc_next->ip) == splt && proc_next->mb1s; + uint64_t pnum = g_cores->pnum; + + salis_step(1); + + if (will_split) { + assert(g_cores->pnum == pnum + 1); + assert(g_cores->plst == pnum); + + switch (g_cores->pnum) { + case 3: + case 4: + case 5: + case 6: + case 7: + check_new_proc(); + break; + default: + assert(false); + } + } + } + + assert(mvec_is_proc_owner(g_cores, proc_fetch(g_cores, 0)->ip, 0)); + assert(g_cores->pnum == 7); + assert(g_cores->pvec[0].sp > MVEC_SIZE); + + salis_free(); + return 0; +} diff --git a/test/ui/v1/allos/vars.py b/test/ui/v1/allos/vars.py new file mode 100644 index 0000000..9c2a9f3 --- /dev/null +++ b/test/ui/v1/allos/vars.py @@ -0,0 +1,3 @@ +flags = set() +defines = set() +links = set() diff --git a/test/ui/v1/ifnzs/ui.c b/test/ui/v1/ifnzs/ui.c new file mode 100644 index 0000000..57e9533 --- /dev/null +++ b/test/ui/v1/ifnzs/ui.c @@ -0,0 +1,46 @@ +#if !defined(COMMAND_NEW) +#error +#endif + +int main(void) { + salis_init(); + + uint64_t next_addr = 0; + + while (mvec_is_proc_owner(g_cores, g_cores->pvec->ip, g_cores->pcur)) { + assert(g_cores->pvec->ip == next_addr); + + if (mvec_get_inst(g_cores, g_cores->pvec->ip) == ifnz) { + switch (mvec_get_inst(g_cores, g_cores->pvec->ip + 1)) { + case nop0: + next_addr += g_cores->pvec->r0x ? 1 : 2; + break; + case nop1: + next_addr += g_cores->pvec->r1x ? 1 : 2; + break; + case nop2: + next_addr += g_cores->pvec->r2x ? 1 : 2; + break; + case nop3: + next_addr += g_cores->pvec->r3x ? 1 : 2; + break; + default: + next_addr += g_cores->pvec->r0x ? 0 : 1; + } + } + + salis_step(1); + next_addr++; + + assert(g_cores->pvec->ip == next_addr); + } + + assert(g_cores->pvec->ip == ANC_SIZE); + assert(g_cores->pvec->r0x == 2); + assert(g_cores->pvec->r1x == 2); + assert(g_cores->pvec->r2x == 2); + assert(g_cores->pvec->r3x == 2); + + salis_free(); + return 0; +} diff --git a/test/ui/v1/ifnzs/vars.py b/test/ui/v1/ifnzs/vars.py new file mode 100644 index 0000000..9c2a9f3 --- /dev/null +++ b/test/ui/v1/ifnzs/vars.py @@ -0,0 +1,3 @@ +flags = set() +defines = set() +links = set() diff --git a/test/ui/v1/ioops/ui.c b/test/ui/v1/ioops/ui.c new file mode 100644 index 0000000..489cb38 --- /dev/null +++ b/test/ui/v1/ioops/ui.c @@ -0,0 +1,55 @@ +#if !defined(COMMAND_NEW) +#error +#endif + +int main(void) { + salis_init(); + + while (mvec_is_proc_owner(g_cores, g_cores->pvec->ip, g_cores->pcur)) { + uint8_t inst = mvec_get_inst(g_cores, g_cores->pvec->ip); + + if (inst != load && inst != wrte) { + salis_step(1); + continue; + } + + uint64_t *regs[2] = { + &g_cores->pvec->r0x, + &g_cores->pvec->r0x, + }; + + for (uint64_t i = 0; i < 2; i++) { + uint8_t rmod = mvec_get_inst(g_cores, g_cores->pvec->ip + 1 + i); + if (rmod == nop0) regs[i] = &g_cores->pvec->r0x; + else if (rmod == nop1) regs[i] = &g_cores->pvec->r1x; + else if (rmod == nop2) regs[i] = &g_cores->pvec->r2x; + else if (rmod == nop3) regs[i] = &g_cores->pvec->r3x; + else break; + } + + if (g_cores->pvec->sp != *regs[0]) { + salis_step(1); + continue; + } + + uint64_t reg_vals[2] = {*regs[0], *regs[1]}; + + assert(g_cores->pvec->sp == *regs[0]); + salis_step(1); + assert(g_cores->pvec->sp == g_cores->pvec->ip); + + switch (inst) { + case load: + assert(*regs[1] == (uint64_t)mvec_get_inst(g_cores, reg_vals[0])); + break; + case wrte: + assert(*regs[0] == reg_vals[0]); + assert(*regs[1] == reg_vals[1]); + assert(mvec_get_inst(g_cores, *regs[0]) == *regs[1] % INST_CAP); + break; + } + } + + salis_free(); + return 0; +} diff --git a/test/ui/v1/ioops/vars.py b/test/ui/v1/ioops/vars.py new file mode 100644 index 0000000..9c2a9f3 --- /dev/null +++ b/test/ui/v1/ioops/vars.py @@ -0,0 +1,3 @@ +flags = set() +defines = set() +links = set() diff --git a/test/ui/v1/jumps/ui.c b/test/ui/v1/jumps/ui.c new file mode 100644 index 0000000..61514f5 --- /dev/null +++ b/test/ui/v1/jumps/ui.c @@ -0,0 +1,21 @@ +#if !defined(COMMAND_NEW) +#error +#endif + +int main(void) { + salis_init(); + + uint8_t lok = loka; + + while (lok != lokp) { + if (mvec_get_inst(g_cores, g_cores->pvec->ip) == lok) { + lok = lok + 1; + } + + salis_step(1); + assert(g_cores->pvec->ip < ANC_SIZE); + } + + salis_free(); + return 0; +} diff --git a/test/ui/v1/jumps/vars.py b/test/ui/v1/jumps/vars.py new file mode 100644 index 0000000..9c2a9f3 --- /dev/null +++ b/test/ui/v1/jumps/vars.py @@ -0,0 +1,3 @@ +flags = set() +defines = set() +links = set() diff --git a/test/ui/v1/mbops/ui.c b/test/ui/v1/mbops/ui.c new file mode 100644 index 0000000..8a92d6f --- /dev/null +++ b/test/ui/v1/mbops/ui.c @@ -0,0 +1,36 @@ +#if !defined(COMMAND_NEW) +#error +#endif + +int main(void) { + salis_init(); + + while (g_cores->pvec->ip < ANC_SIZE) { + bool on_swap = mvec_get_inst(g_cores, g_cores->pvec->ip) == bswp; + bool on_clear = mvec_get_inst(g_cores, g_cores->pvec->ip) == bclr; + + uint64_t mb0a = g_cores->pvec->mb0a; + uint64_t mb0s = g_cores->pvec->mb0s; + uint64_t mb1a = g_cores->pvec->mb1a; + uint64_t mb1s = g_cores->pvec->mb1s; + + salis_step(1); + + if (on_swap) { + if (mb1s) { + assert(g_cores->pvec->mb0a == mb1a); + assert(g_cores->pvec->mb0s == mb1s); + assert(g_cores->pvec->mb1a == mb0a); + assert(g_cores->pvec->mb1s == mb0s); + } + } + + if (on_clear) { + assert(g_cores->pvec->mb1a == 0); + assert(g_cores->pvec->mb1s == 0); + } + } + + salis_free(); + return 0; +} diff --git a/test/ui/v1/mbops/vars.py b/test/ui/v1/mbops/vars.py new file mode 100644 index 0000000..9c2a9f3 --- /dev/null +++ b/test/ui/v1/mbops/vars.py @@ -0,0 +1,3 @@ +flags = set() +defines = set() +links = set() diff --git a/test/ui/v1/stack/ui.c b/test/ui/v1/stack/ui.c new file mode 100644 index 0000000..1ad047e --- /dev/null +++ b/test/ui/v1/stack/ui.c @@ -0,0 +1,75 @@ +#if !defined(COMMAND_NEW) +#error +#endif + +int main(void) { + salis_init(); + + while (mvec_is_proc_owner(g_cores, g_cores->pvec->ip, g_cores->pcur)) { + uint8_t inst = mvec_get_inst(g_cores, g_cores->pvec->ip); + + if (inst != pshn && inst != popn) { + salis_step(1); + continue; + } + + uint64_t *reg = &g_cores->pvec->r0x; + + switch (mvec_get_inst(g_cores, g_cores->pvec->ip + 1)) { + case nop0: + reg = &g_cores->pvec->r0x; + break; + case nop1: + reg = &g_cores->pvec->r1x; + break; + case nop2: + reg = &g_cores->pvec->r2x; + break; + case nop3: + reg = &g_cores->pvec->r3x; + break; + } + + uint64_t reg_val = *reg; + uint64_t stack_val[8] = { + g_cores->pvec->s0, + g_cores->pvec->s1, + g_cores->pvec->s2, + g_cores->pvec->s3, + g_cores->pvec->s4, + g_cores->pvec->s5, + g_cores->pvec->s6, + g_cores->pvec->s7, + }; + + salis_step(1); + + switch (inst) { + case pshn: + assert(*reg == reg_val); + assert(g_cores->pvec->s0 == *reg); + assert(g_cores->pvec->s1 == stack_val[0]); + assert(g_cores->pvec->s2 == stack_val[1]); + assert(g_cores->pvec->s3 == stack_val[2]); + assert(g_cores->pvec->s4 == stack_val[3]); + assert(g_cores->pvec->s5 == stack_val[4]); + assert(g_cores->pvec->s6 == stack_val[5]); + assert(g_cores->pvec->s7 == stack_val[6]); + break; + case popn: + assert(*reg == stack_val[0]); + assert(g_cores->pvec->s0 == stack_val[1]); + assert(g_cores->pvec->s1 == stack_val[2]); + assert(g_cores->pvec->s2 == stack_val[3]); + assert(g_cores->pvec->s3 == stack_val[4]); + assert(g_cores->pvec->s4 == stack_val[5]); + assert(g_cores->pvec->s5 == stack_val[6]); + assert(g_cores->pvec->s6 == stack_val[7]); + assert(g_cores->pvec->s7 == 0); + break; + } + } + + salis_free(); + return 0; +} diff --git a/test/ui/v1/stack/vars.py b/test/ui/v1/stack/vars.py new file mode 100644 index 0000000..9c2a9f3 --- /dev/null +++ b/test/ui/v1/stack/vars.py @@ -0,0 +1,3 @@ +flags = set() +defines = set() +links = set() diff --git a/ui/curses/ui.c b/ui/curses/ui.c index 9d253a3..ace7bf9 100644 --- a/ui/curses/ui.c +++ b/ui/curses/ui.c @@ -255,7 +255,10 @@ void gfx_render_mbst(const struct Core *core, uint64_t pos, uint64_t zoom) { uint64_t mb1a = arch_proc_mb1_addr(core, pix); gfx_accumulate_pixel(pos, zoom, mb0a, g_gfx_mbst); - gfx_accumulate_pixel(pos, zoom, mb1a, g_gfx_mbst); + + if (arch_proc_mb1_size(core, pix)) { + gfx_accumulate_pixel(pos, zoom, mb1a, g_gfx_mbst); + } } } @@ -418,12 +421,6 @@ void tui_uld_field(int l, const char *label, uint64_t value) { tui_line(false, l, PAIR_NORMAL, A_NORMAL, "%-4s : %#18ld", label, value); } -void tui_float_field(int l, const char *label, float value) { - assert(label); - assert(strlen(label) <= 4); - tui_line(false, l, PAIR_NORMAL, A_NORMAL, "%-4s : %18.1f", label, value); -} - void tui_print_core(int l) { tui_line(false, ++l, PAIR_HEADER, A_BOLD, "CORE [%d]", g_core); tui_ulx_field(++l, "cycl", g_cores[g_core].cycl); @@ -928,7 +925,7 @@ void tui_print(void) { tui_ulx_field(l++, "step", g_steps); tui_ulx_field(l++, "sync", g_syncs); tui_ulx_field(l++, "step", g_step_block); - tui_float_field(l++, "stps", g_steps_per_sec); + tui_ulx_field(l++, "stps", (uint64_t)g_steps_per_sec); switch (g_page) { case PAGE_CORE: |