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#if !defined(COMMAND_NEW)
#error
#endif
int main(void) {
salis_init();
while (mvec_is_proc_owner(g_cores, g_cores->pvec->ip, g_cores->pcur)) {
uint8_t inst = mvec_get_inst(g_cores, g_cores->pvec->ip);
if (inst != addn && inst != subn && inst != muln && inst != divn) {
salis_step(1);
continue;
}
uint64_t *regs[3] = {
&g_cores->pvec->r0x,
&g_cores->pvec->r0x,
&g_cores->pvec->r0x,
};
for (uint64_t i = 0; i < 3; i++) {
uint8_t rmod = mvec_get_inst(g_cores, g_cores->pvec->ip + 1 + i);
if (rmod == nop0) regs[i] = &g_cores->pvec->r0x;
else if (rmod == nop1) regs[i] = &g_cores->pvec->r1x;
else if (rmod == nop2) regs[i] = &g_cores->pvec->r2x;
else if (rmod == nop3) regs[i] = &g_cores->pvec->r3x;
else break;
}
uint64_t reg_vals[3] = {*regs[0], *regs[1], *regs[2]};
salis_step(1);
uint64_t result = *regs[0];
switch (inst) {
case addn:
assert(result == reg_vals[1] + reg_vals[2]);
break;
case subn:
assert(result == reg_vals[1] - reg_vals[2]);
break;
case muln:
assert(result == reg_vals[1] * reg_vals[2]);
break;
case divn:
if (reg_vals[2] != 0) {
assert(result == reg_vals[1] / reg_vals[2]);
} else {
assert(*regs[0] == reg_vals[0]);
assert(*regs[1] == reg_vals[1]);
assert(*regs[2] == reg_vals[2]);
}
break;
}
}
salis_free();
return 0;
}
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